1. Field of the Invention
The present invention relates to an information processing apparatus and, more particularly, to an information processing apparatus having a power control function.
2. Description of the Prior Art
An information processing apparatus such as a microprocessor having a power saving control function has been known (Japanese Unexamined Patent Publication Nos. 63-26716 and 3-10306). FIG. 1 is a circuit diagram showing an overall arrangement of this conventional information processing apparatus. In the conventional information processing apparatus, an instruction designated by a program counter 1 is loaded from an instruction memory 2 into an instruction register 3 in synchronism with a clock CL1. An instruction decoder 4 decodes the instruction loaded into the instruction register 3. As a result, a function block selection signal associated with the execution of the instruction is activated in synchronism with a clock CL2.
The logic of each active output signal from the instruction decoder 4 is inverted by a corresponding one of inverters 5a to 5n. Each inverted signal is then input to one input terminal of a corresponding one of two-input AND circuits 6a to 6n. Meanwhile, a clock CL3, for determining the operation timing of each function block, is commonly input to the other input terminal of each of the two-input AND circuits 6a to 6n through a buffer 10.
The output signals from the two-input AND circuits 6a to 6n are respectively supplied to function blocks 8a to 8n through buffers 7a to 7n arranged in correspondence with the two-input AND circuits 6a to 6n. With this connection, the clock CL3 is supplied to only the function block, of the function blocks 8a to 8n, which is used for each instruction, but the remaining function blocks that are not used do not operate. This can reduce the overall power consumption.
Although not described in the above reference, each of the function blocks 8a to 8n does not operate singly, and the respective function blocks operate in association with each other in the actual information processing apparatus. For this reason, the apparatus uses a inter-function-block control signal 9. The operation of the inter-function-block control signal 9 will be described for a case where the contents of the memory are loaded into the instruction register. In this case, a register circuit and a memory access circuit serve as function blocks.
When an instruction is decoded, a clock is supplied to these two function blocks to start the operation. The memory access circuit as one function block outputs a memory read request to the outside of the information processing apparatus, waits for a response from the outside, and receives data. The memory access circuit then writes the data in the register by using the register circuit as the other function block. In this case, memory access depends on the external state (for example, in the case of a dynamic random access memory (DRAM), no response is received during memory refresh operation).
The memory access circuit must therefore keep operating (monitoring) to prepare for the reception of data at any moment. The memory access circuit must also notify the register circuit that the data has been received (or will be received). The inter-function-block control signal 9 includes a control signal for the notification of such a state between these function blocks.
An information processing apparatus using a semiconductor device takes two types of circuit arrangements, namely a static circuit and a dynamic circuit. The static circuit establishes a stable state by using transistors, and stably operates independently of the clocks. The dynamic circuit uses interconnection capacitances. More specifically, this dynamic circuit uses the charge stored in the capacitances to suppress the number of transistors to be used, thereby attaining a high integration degree. Since the dynamic circuit uses the charge in the interconnection capacitances, the circuit stops operating a given period of time after the charge is discharged. For this reason, the dynamic circuit has a lower operating frequency limit.
In the above conventional information processing apparatus, clock control on the respective function blocks is determined by only decoding of instructions, but does not depend on the internal state of respective function blocks. For this reason, unnecessary function blocks may operate to consume excess power. In the above case of memory read access, the register function block in the memory access completion wait state is an unnecessary block.
In the information processing apparatus having the semiconductor circuit using the dynamic circuit, because of the lower operating frequency limit described above, when the clock is completely stopped, the internal state of a function block changes. As a result, the block may not operate properly.